VHDL System-Level Specification and Partitioning in a Hardwarelsoftware Co-Synthesis Environment

This paper deals with the problems of system-level specijcation and partitioning in hardwarelsoftware co-design. Itfirst discusses the implication of using VHDL as an implementation-independent specification language. A message passing communication mechanism is proposed to relax the strict synchronization imposed by the simulation-based semantics of VHDL. A partitioning technique is then described which is used to partition the VHDL specifiation into a hardware part and a software part. The partitioning is carried out during the compilation process of VHDL into a design representation which identifies the hardwarelsojlware boundary, while capturing hardware and software in a uniform way to allow eficient co-synthesis of both parts. The VHDL compiler and the partitioning algorithm function as the front end of a hardwarelsoftware co-synthesis environment which is built on the design representation.